Typical state of the art semiconductor device packaging uses high density interconnection structures in which typically unpackaged integrated circuit (IC) chips or bare die are connected both mechanically and electrically onto a single substrate of silicon, ceramic, or epoxy glass laminate. The choice of interconnection technique, substrate material, and bonding process steps e.g. cleaning, all play significant roles in defining the overall assembly technique and its influence on MCM cost and reliability. A variety of interconnection techniques have been used in the microelectronics industry to assemble bare die onto the MCM substrates. These substrates function as both structural support and as the "fabric" for the electrical interconnections between ICs. Typically MCMs are assembled using one of a variety of known techniques, i.e. wire bonding, tape automated bonding (TAB) and flip-chip soldering.
In general, the design of the MCM package depends on the particular capabilities of the manufacturer, the MCM architecture, the relative cost of materials and the required I/O configuration and density. In turn, the choice of interconnection technique and cleaning processes play a major role in defining the assembly process required for high yield, and product reliability.
The most common, and nominally the lowest cost, interconnection technique is wire bonding. However, wire bond connections have the disadvantage of having a large footprint, which results in a large substrate and a necessarily less compact MCM. As is well known in electronics manufacturing, increased size of any feature in the assembly translates directly into added cost. Moreover in an MCM module, increasing the size of the module increases the length of interconnects, leading to increased lead inductance and resistance, and a degradation in electrical performance. Furthermore, a typical wire bonding apparatus, e.g. a stitch bonder, makes bonds one at a time, a time consuming operation even with the advanced high speed bonders available today.
TAB bonding has the advantages of both a smaller footprint and of partial batch processing. However, TAB assembly generally requires different tooling for each IC design, adding significant cost to this bonding technique. Moreover, TAB assembly is restricted to interconnection of perimeter I/O arrays thus limiting the IC design flexibility. Perimeter I/O pads typically have higher pitches and correspondingly lower overall I/O densities than the area I/O arrays that can be used with flip-chip solder bonding. Also TAB bonded interconnections typically show higher capacitance and greater parasitic inductance than flip-chip bonded interconnections.
It is now recognized that flip-chip bonding provides the best performance at the highest I/O density for either perimeter or area I/O arrays. Furthermore, flip-chip bonding is inherently a batch assembly process which facilitates high speed, high through-put manufacture. However, for a variety of reasons, flip-chip MCM assembly is usually considered to be the most expensive of the known assembly techniques. This is especially true for high performance MCM designs which often use multi-layer co-fired ceramics (MCM-C), or deposited thin film ceramic or silicon substrates (MCM-D) as the interconnection substrate. The less expensive alternative is a typical printed wiring board, i.e epoxy-glass fiber laminate. However, as the I/O count and density increases in state of the art assemblies, silicon becomes more cost competitive, and represents the interconnection substrate of choice for high performance applications.
Assembly of electronics packages using flip-chip techniques is a dominant technology, especially in the manufacture of computers and computer peripherals. It is also widely used in the assembly of electronics and photonics packages for communication network products. The essence of flip-chip assembly is the attachment of semiconductor substrates "upside down" on an interconnection substrate such as a silicon wafer, ceramic substrate, or printed circuit board. The attachment means is typically solder, in the form of balls, pads, or bumps (generically referred to hereinafter as bumps). Solder bumps may be applied to the semiconductor chip, or to the interconnection substrate, or to both. In the bonding operation, the chip is placed in contact with the substrate and the solder is heated to reflow the solder and attach the chip to the substrate. For successful bonding, it is necessary that the sites to which the solder is bonded it wettable by the solder.
The metal interconnection pattern typically used for integrated circuits boards or cards is aluminum. While techniques for soldering directly to aluminum have been tried it is well known and accepted that aluminum is not a desirable material to solder. Consequently the practice in the industry is to apply a metal coating on the aluminum contact pads, and apply the solder bump or pad to the coating. The metal coating is typically referred to as Under Bump Metallization (UBM).
The metal or metals used in UBM technology must adhere well to aluminum, be wettable by typical tin solder formulations, and be highly conductive. A structure meeting these requirements is a composite of chromium and copper. Chromium is deposited first, to adhere to the aluminum, and copper is applied over the chromium to provide a solder wettable surface. Chromium is known to adhere well to a variety of materials, organic as well as inorganic. Accordingly it adheres well to dielectric materials, e.g. SiO.sub.2, SINCAPS, polyimide, etc., commonly used in IC processing, as well as to metals such as copper and aluminum. However, solder alloys dissolve copper and de-wet from chromium. Therefore, a thin layer of copper directly on chromium will dissolve into the molten solder and then the solder will de-wet from the chromium layer. To insure interface integrity between the solder and the UBM, a composite or alloy layer of chromium and copper is typically used between the chromium and copper layers.
The aforementioned layers are conventionally sputtered, so several options for depositing them are conveniently available. The layer can be sputtered from an alloy target. It can be sputtered using a chromium target, then changing to a copper target. Or it can be sputtered using separate chromium and copper targets, and transitioning between the two. The latter option produces a layer with a graded composition, and is a preferred technique.
In forming the structure just described the accepted practice is to use an additive process for selective deposition of the composite layer. Additive processes are well known and are usually implemented using lift-off techniques. However, the lift-off process has an inherent incompatibility with the preferred technique for depositing the UBM, i.e. sputtering. In sputtering, the UMB the substrate reaches temperatures exceeding 100.degree. C. At these temperatures the photoresist used for lift-off undergoes dimensional distortion, and the edge acuity of the photoresist pattern deteriorates. Moreover, to improve adhesion of the UBM to the underlying substrate it is customary to back sputter the surface to roughen it. In this process the substrate and the photoresist are also heated to temperatures above 100.degree. C., adding further incompatibility to the process.